#include <stdint.h>
#include <pbl/drivers/flash.h>
#include <pbl/util/bits.h>

Data Structures
struct	pbl_flash_nor_otp
	Organization of the security registers that make up the user OTP area. More...

struct	pbl_flash_nor_part
	A NOR part. More...

Macros
#define	PBL_FLASH_NOR_OTP(_len, _n, _base, _offset, _lb_bit)
	Initializer for a struct pbl_flash_nor_otp.

#define	PBL_FLASH_NOR_F_4B_OPCODES PBL_BIT(0)
	The part has 4-byte address opcodes (13h, 0Ch, 12h, 34h, 21h, DCh, ...).

Commands
#define	PBL_FLASH_NOR_CMD_WREN 0x06U
	Write enable.

#define	PBL_FLASH_NOR_CMD_RDSR 0x05U
	Read status register 1.

#define	PBL_FLASH_NOR_CMD_RDSR2 0x35U
	Read status register 2.

#define	PBL_FLASH_NOR_CMD_WRSR 0x01U
	Write status registers 1 and 2.

#define	PBL_FLASH_NOR_CMD_WRSR2 0x31U
	Write status register 2.

#define	PBL_FLASH_NOR_CMD_RDID 0x9FU
	Read JEDEC ID.

#define	PBL_FLASH_NOR_CMD_RDSFDP 0x5AU
	Read SFDP.

#define	PBL_FLASH_NOR_CMD_FAST_READ 0x0BU
	Fast read (1-1-1).

#define	PBL_FLASH_NOR_CMD_PP 0x02U
	Page program (1-1-1).

#define	PBL_FLASH_NOR_CMD_PP_1_1_4 0x32U
	Quad input page program (1-1-4).

#define	PBL_FLASH_NOR_CMD_SE 0x20U
	4 KiB erase.

#define	PBL_FLASH_NOR_CMD_BE 0xD8U
	64 KiB erase.

#define	PBL_FLASH_NOR_CMD_SE_4B 0x21U
	4 KiB erase, 4-byte address.

#define	PBL_FLASH_NOR_CMD_BE_4B 0xDCU
	64 KiB erase, 4-byte address.

#define	PBL_FLASH_NOR_CMD_EN4B 0xB7U
	Enter 4-byte address mode.

#define	PBL_FLASH_NOR_CMD_EX4B 0xE9U
	Exit 4-byte address mode.

#define	PBL_FLASH_NOR_CMD_RSTEN 0x66U
	Reset enable.

#define	PBL_FLASH_NOR_CMD_RST 0x99U
	Reset.

#define	PBL_FLASH_NOR_CMD_SUSPEND 0x75U
	Erase suspend.

#define	PBL_FLASH_NOR_CMD_RESUME 0x7AU
	Erase resume.

#define	PBL_FLASH_NOR_CMD_DPD 0xB9U
	Enter deep power-down.

#define	PBL_FLASH_NOR_CMD_RDPD 0xABU
	Release from deep power-down.

#define	PBL_FLASH_NOR_CMD_ERSCUR 0x44U
	Erase a security register.

#define	PBL_FLASH_NOR_CMD_PRSCUR 0x42U
	Program a security register.

#define	PBL_FLASH_NOR_CMD_RDSCUR 0x48U
	Read a security register.

Status register bits
#define	PBL_FLASH_NOR_SR_WIP PBL_BIT(0)
	Status register 1: write in progress.

#define	PBL_FLASH_NOR_SR_QE PBL_BIT(6)
	Status register 1: quad enable, on PBL_FLASH_NOR_QE_SR1_BIT6 parts.

#define	PBL_FLASH_NOR_SR2_QE PBL_BIT(1)
	Status register 2: quad enable, on the other parts with one.

#define	PBL_FLASH_NOR_SR2_SUS PBL_BIT(7)
	Status register 2: erase suspended.

Enumerations
enum	pbl_flash_nor_qe { PBL_FLASH_NOR_QE_NONE , PBL_FLASH_NOR_QE_SR2_BIT1_WR_SR1 , PBL_FLASH_NOR_QE_SR1_BIT6 , PBL_FLASH_NOR_QE_SR2_BIT1 }
	Quad enable bit location, as in JESD216 BFPT DWORD 15. More...

Variables
const struct pbl_flash_nor_part	pbl_flash_nor_gd25lq255e
	GigaDevice GD25LQ255E.

const struct pbl_flash_nor_part	pbl_flash_nor_gd25q256e
	GigaDevice GD25Q256E.

Data Structures

Macros

Enumerations

Variables