Description of the SPI NOR parts boards are fitted with. More...

Data Structures
struct	pbl_flash_nor_otp
	Organization of the security registers that make up the user OTP area. More...

struct	pbl_flash_nor_part
	A NOR part. More...

Macros
#define	PBL_FLASH_NOR_OTP(_len, _n, _base, _offset, _lb_bit)
	Initializer for a struct pbl_flash_nor_otp.

#define	PBL_FLASH_NOR_F_4B_OPCODES PBL_BIT(0)
	The part has 4-byte address opcodes (13h, 0Ch, 12h, 34h, 21h, DCh, ...).

Enumerations
enum	pbl_flash_nor_qe { PBL_FLASH_NOR_QE_NONE , PBL_FLASH_NOR_QE_SR2_BIT1_WR_SR1 , PBL_FLASH_NOR_QE_SR1_BIT6 , PBL_FLASH_NOR_QE_SR2_BIT1 }
	Quad enable bit location, as in JESD216 BFPT DWORD 15. More...

Variables
const struct pbl_flash_nor_part	pbl_flash_nor_gd25lq255e
	GigaDevice GD25LQ255E.

const struct pbl_flash_nor_part	pbl_flash_nor_gd25q256e
	GigaDevice GD25Q256E.

Commands
#define	PBL_FLASH_NOR_CMD_WREN 0x06U
	Write enable.

#define	PBL_FLASH_NOR_CMD_RDSR 0x05U
	Read status register 1.

#define	PBL_FLASH_NOR_CMD_RDSR2 0x35U
	Read status register 2.

#define	PBL_FLASH_NOR_CMD_WRSR 0x01U
	Write status registers 1 and 2.

#define	PBL_FLASH_NOR_CMD_WRSR2 0x31U
	Write status register 2.

#define	PBL_FLASH_NOR_CMD_RDID 0x9FU
	Read JEDEC ID.

#define	PBL_FLASH_NOR_CMD_RDSFDP 0x5AU
	Read SFDP.

#define	PBL_FLASH_NOR_CMD_FAST_READ 0x0BU
	Fast read (1-1-1).

#define	PBL_FLASH_NOR_CMD_PP 0x02U
	Page program (1-1-1).

#define	PBL_FLASH_NOR_CMD_PP_1_1_4 0x32U
	Quad input page program (1-1-4).

#define	PBL_FLASH_NOR_CMD_SE 0x20U
	4 KiB erase.

#define	PBL_FLASH_NOR_CMD_BE 0xD8U
	64 KiB erase.

#define	PBL_FLASH_NOR_CMD_SE_4B 0x21U
	4 KiB erase, 4-byte address.

#define	PBL_FLASH_NOR_CMD_BE_4B 0xDCU
	64 KiB erase, 4-byte address.

#define	PBL_FLASH_NOR_CMD_EN4B 0xB7U
	Enter 4-byte address mode.

#define	PBL_FLASH_NOR_CMD_EX4B 0xE9U
	Exit 4-byte address mode.

#define	PBL_FLASH_NOR_CMD_RSTEN 0x66U
	Reset enable.

#define	PBL_FLASH_NOR_CMD_RST 0x99U
	Reset.

#define	PBL_FLASH_NOR_CMD_SUSPEND 0x75U
	Erase suspend.

#define	PBL_FLASH_NOR_CMD_RESUME 0x7AU
	Erase resume.

#define	PBL_FLASH_NOR_CMD_DPD 0xB9U
	Enter deep power-down.

#define	PBL_FLASH_NOR_CMD_RDPD 0xABU
	Release from deep power-down.

#define	PBL_FLASH_NOR_CMD_ERSCUR 0x44U
	Erase a security register.

#define	PBL_FLASH_NOR_CMD_PRSCUR 0x42U
	Program a security register.

#define	PBL_FLASH_NOR_CMD_RDSCUR 0x48U
	Read a security register.

Status register bits
#define	PBL_FLASH_NOR_SR_WIP PBL_BIT(0)
	Status register 1: write in progress.

#define	PBL_FLASH_NOR_SR_QE PBL_BIT(6)
	Status register 1: quad enable, on PBL_FLASH_NOR_QE_SR1_BIT6 parts.

#define	PBL_FLASH_NOR_SR2_QE PBL_BIT(1)
	Status register 2: quad enable, on the other parts with one.

#define	PBL_FLASH_NOR_SR2_SUS PBL_BIT(7)
	Status register 2: erase suspended.

Detailed Description

Description of the SPI NOR parts boards are fitted with.

Parts share the command set below; a part only describes what differs between them.

Data Structure Documentation

◆ pbl_flash_nor_otp

struct pbl_flash_nor_otp

Organization of the security registers that make up the user OTP area.

Region i is the security register at base + i * offset, read with 48h, programmed with 42h and erased with 44h, and locked by status register 2 bit lb_bit + i.

Data Fields
uint32_t	base	Address of the first region.
struct pbl_flash_otp_info	info	Region size and count.
uint8_t	lb_bit	Status register 2 lock bit of the first region.
uint32_t	offset	Distance between regions.

◆ pbl_flash_nor_part

struct pbl_flash_nor_part

A NOR part.

Data Fields
uint16_t	dpd_enter_us	Time to enter deep power-down, in microseconds.
uint16_t	dpd_exit_us	Time to leave deep power-down, in microseconds.
uint32_t	flags	Flags, `PBL_FLASH_NOR_F_*`.
struct pbl_flash_geometry	geometry	Geometry.
uint32_t	id	JEDEC ID as read, manufacturer in the least significant byte.
const char *	name	Name.
struct pbl_flash_nor_otp	otp	User OTP area.
enum pbl_flash_nor_qe	qe	Quad enable bit location, and how status register 2 is written. Overrides SFDP.
uint16_t	reset_ms	Time from a reset until commands are accepted, in milliseconds.
uint16_t	resume_us	Shortest time from an erase resume to the next suspend, in microseconds.
uint8_t	sr1_bp_mask	Block protection bits of status register 1, cleared at init.
uint16_t	suspend_us	Time from an erase suspend until reads are allowed, in microseconds.

Macro Definition Documentation

◆ PBL_FLASH_NOR_CMD_BE

#define PBL_FLASH_NOR_CMD_BE 0xD8U

64 KiB erase.

◆ PBL_FLASH_NOR_CMD_BE_4B

#define PBL_FLASH_NOR_CMD_BE_4B 0xDCU

64 KiB erase, 4-byte address.

◆ PBL_FLASH_NOR_CMD_DPD

#define PBL_FLASH_NOR_CMD_DPD 0xB9U

Enter deep power-down.

◆ PBL_FLASH_NOR_CMD_EN4B

#define PBL_FLASH_NOR_CMD_EN4B 0xB7U

Enter 4-byte address mode.

◆ PBL_FLASH_NOR_CMD_ERSCUR

#define PBL_FLASH_NOR_CMD_ERSCUR 0x44U

Erase a security register.

◆ PBL_FLASH_NOR_CMD_EX4B

#define PBL_FLASH_NOR_CMD_EX4B 0xE9U

Exit 4-byte address mode.

◆ PBL_FLASH_NOR_CMD_FAST_READ

#define PBL_FLASH_NOR_CMD_FAST_READ 0x0BU

Fast read (1-1-1).

◆ PBL_FLASH_NOR_CMD_PP

#define PBL_FLASH_NOR_CMD_PP 0x02U

Page program (1-1-1).

◆ PBL_FLASH_NOR_CMD_PP_1_1_4

#define PBL_FLASH_NOR_CMD_PP_1_1_4 0x32U

Quad input page program (1-1-4).

◆ PBL_FLASH_NOR_CMD_PRSCUR

#define PBL_FLASH_NOR_CMD_PRSCUR 0x42U

Program a security register.

◆ PBL_FLASH_NOR_CMD_RDID

#define PBL_FLASH_NOR_CMD_RDID 0x9FU

Read JEDEC ID.

◆ PBL_FLASH_NOR_CMD_RDPD

#define PBL_FLASH_NOR_CMD_RDPD 0xABU

Release from deep power-down.

◆ PBL_FLASH_NOR_CMD_RDSCUR

#define PBL_FLASH_NOR_CMD_RDSCUR 0x48U

Read a security register.

◆ PBL_FLASH_NOR_CMD_RDSFDP

#define PBL_FLASH_NOR_CMD_RDSFDP 0x5AU

Read SFDP.

◆ PBL_FLASH_NOR_CMD_RDSR

#define PBL_FLASH_NOR_CMD_RDSR 0x05U

Read status register 1.

◆ PBL_FLASH_NOR_CMD_RDSR2

#define PBL_FLASH_NOR_CMD_RDSR2 0x35U

Read status register 2.

◆ PBL_FLASH_NOR_CMD_RESUME

#define PBL_FLASH_NOR_CMD_RESUME 0x7AU

Erase resume.

◆ PBL_FLASH_NOR_CMD_RST

#define PBL_FLASH_NOR_CMD_RST 0x99U

Reset.

◆ PBL_FLASH_NOR_CMD_RSTEN

#define PBL_FLASH_NOR_CMD_RSTEN 0x66U

Reset enable.

◆ PBL_FLASH_NOR_CMD_SE

#define PBL_FLASH_NOR_CMD_SE 0x20U

4 KiB erase.

◆ PBL_FLASH_NOR_CMD_SE_4B

#define PBL_FLASH_NOR_CMD_SE_4B 0x21U

4 KiB erase, 4-byte address.

◆ PBL_FLASH_NOR_CMD_SUSPEND

#define PBL_FLASH_NOR_CMD_SUSPEND 0x75U

Erase suspend.

◆ PBL_FLASH_NOR_CMD_WREN

#define PBL_FLASH_NOR_CMD_WREN 0x06U

Write enable.

◆ PBL_FLASH_NOR_CMD_WRSR

#define PBL_FLASH_NOR_CMD_WRSR 0x01U

Write status registers 1 and 2.

◆ PBL_FLASH_NOR_CMD_WRSR2

#define PBL_FLASH_NOR_CMD_WRSR2 0x31U

Write status register 2.

◆ PBL_FLASH_NOR_F_4B_OPCODES

#define PBL_FLASH_NOR_F_4B_OPCODES PBL_BIT(0)

The part has 4-byte address opcodes (13h, 0Ch, 12h, 34h, 21h, DCh, ...).

◆ PBL_FLASH_NOR_OTP

#define PBL_FLASH_NOR_OTP	(	_len,
		_n,
		_base,
		_offset,
		_lb_bit
	)

Value:

  {                                                          \
    .info = {.region_len = (_len), .n_regions = (_n)},       \
    .base = (_base),                                         \
    .offset = (_offset),                                     \
    .lb_bit = (_lb_bit),                                     \
  }

Initializer for a struct pbl_flash_nor_otp.

Parameters

_len	Region size, in bytes.
_n	Number of regions.
_base	Address of the first region.
_offset	Distance between regions.
_lb_bit	Status register 2 lock bit of the first region.

◆ PBL_FLASH_NOR_SR2_QE

#define PBL_FLASH_NOR_SR2_QE PBL_BIT(1)

Status register 2: quad enable, on the other parts with one.

◆ PBL_FLASH_NOR_SR2_SUS

#define PBL_FLASH_NOR_SR2_SUS PBL_BIT(7)

Status register 2: erase suspended.

◆ PBL_FLASH_NOR_SR_QE

#define PBL_FLASH_NOR_SR_QE PBL_BIT(6)

Status register 1: quad enable, on PBL_FLASH_NOR_QE_SR1_BIT6 parts.

◆ PBL_FLASH_NOR_SR_WIP

#define PBL_FLASH_NOR_SR_WIP PBL_BIT(0)

Status register 1: write in progress.

Enumeration Type Documentation

◆ pbl_flash_nor_qe

enum pbl_flash_nor_qe

Quad enable bit location, as in JESD216 BFPT DWORD 15.

Enumerator
PBL_FLASH_NOR_QE_NONE	No quad enable bit.
PBL_FLASH_NOR_QE_SR2_BIT1_WR_SR1	Status register 2 bit 1, written together with status register 1.
PBL_FLASH_NOR_QE_SR1_BIT6	Status register 1 bit 6.
PBL_FLASH_NOR_QE_SR2_BIT1	Status register 2 bit 1, written on its own.

Variable Documentation

◆ pbl_flash_nor_gd25lq255e

const struct pbl_flash_nor_part pbl_flash_nor_gd25lq255e

extern

GigaDevice GD25LQ255E.

◆ pbl_flash_nor_gd25q256e

const struct pbl_flash_nor_part pbl_flash_nor_gd25q256e