PebbleOS
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MMIO

Memory-mapped I/O register access. More...

Functions

static uint8_t pbl_readb (uintptr_t addr)
 Read an 8-bit register.
 
static uint16_t pbl_readw (uintptr_t addr)
 Read a 16-bit register.
 
static uint32_t pbl_readl (uintptr_t addr)
 Read a 32-bit register.
 
static void pbl_writeb (uint8_t val, uintptr_t addr)
 Write an 8-bit register.
 
static void pbl_writew (uint16_t val, uintptr_t addr)
 Write a 16-bit register.
 
static void pbl_writel (uint32_t val, uintptr_t addr)
 Write a 32-bit register.
 
static void pbl_modifyb (uint8_t clear, uint8_t set, uintptr_t addr)
 Atomically clear and set bits of a shared 8-bit register.
 
static void pbl_modifyw (uint16_t clear, uint16_t set, uintptr_t addr)
 Atomically clear and set bits of a shared 16-bit register.
 
static void pbl_modifyl (uint32_t clear, uint32_t set, uintptr_t addr)
 Atomically clear and set bits of a shared 32-bit register.
 

Detailed Description

Memory-mapped I/O register access.

Each access is a single load or store of the given width. Accesses to the same device stay in program order, but are not ordered against normal memory: a driver that hands memory to a DMA engine orders them with pbl_wmb() and pbl_rmb():

buf[0] = cmd;
pbl_writel(DMA_START, cfg->base + DMA_CTRL);
while ((pbl_readl(cfg->base + DMA_STATUS) & STATUS_DONE) == 0U) {
}
reply = buf[1];
static void pbl_rmb(void)
Order earlier memory and device reads before later ones.
Definition barrier.h:28
static void pbl_wmb(void)
Order earlier memory and device writes before later ones.
Definition barrier.h:33
static uint32_t pbl_readl(uintptr_t addr)
Read a 32-bit register.
Definition mmio.h:67
static void pbl_writel(uint32_t val, uintptr_t addr)
Write a 32-bit register.
Definition mmio.h:97

Registers shared between drivers, such as clock gates or system control bits, are updated with pbl_modifyl() and friends, which read, modify and write under pbl_irq_lock(). Registers owned by a single driver, and writes that are atomic in hardware (set/clear registers, write-1-to-clear flags), can use the plain accessors. Interrupts flagged PBL_IRQ_ZERO_LATENCY are not masked by the lock and must not touch shared registers.

Function Documentation

◆ pbl_modifyb()

static void pbl_modifyb ( uint8_t  clear,
uint8_t  set,
uintptr_t  addr 
)
static

Atomically clear and set bits of a shared 8-bit register.

Parameters
clearBits to clear.
setBits to set, applied after clear.
addrRegister address.

References pbl_irq_lock(), and pbl_irq_unlock().

◆ pbl_modifyl()

static void pbl_modifyl ( uint32_t  clear,
uint32_t  set,
uintptr_t  addr 
)
static

Atomically clear and set bits of a shared 32-bit register.

Parameters
clearBits to clear.
setBits to set, applied after clear.
addrRegister address, 4-byte aligned.

References pbl_irq_lock(), and pbl_irq_unlock().

◆ pbl_modifyw()

static void pbl_modifyw ( uint16_t  clear,
uint16_t  set,
uintptr_t  addr 
)
static

Atomically clear and set bits of a shared 16-bit register.

Parameters
clearBits to clear.
setBits to set, applied after clear.
addrRegister address, 2-byte aligned.

References pbl_irq_lock(), and pbl_irq_unlock().

◆ pbl_readb()

static uint8_t pbl_readb ( uintptr_t  addr)
static

Read an 8-bit register.

Parameters
addrRegister address.
Returns
Register value.

◆ pbl_readl()

static uint32_t pbl_readl ( uintptr_t  addr)
static

Read a 32-bit register.

Parameters
addrRegister address, 4-byte aligned.
Returns
Register value.

◆ pbl_readw()

static uint16_t pbl_readw ( uintptr_t  addr)
static

Read a 16-bit register.

Parameters
addrRegister address, 2-byte aligned.
Returns
Register value.

◆ pbl_writeb()

static void pbl_writeb ( uint8_t  val,
uintptr_t  addr 
)
static

Write an 8-bit register.

Parameters
valValue to write.
addrRegister address.

◆ pbl_writel()

static void pbl_writel ( uint32_t  val,
uintptr_t  addr 
)
static

Write a 32-bit register.

Parameters
valValue to write.
addrRegister address, 4-byte aligned.

◆ pbl_writew()

static void pbl_writew ( uint16_t  val,
uintptr_t  addr 
)
static

Write a 16-bit register.

Parameters
valValue to write.
addrRegister address, 2-byte aligned.