Cache maintenance

Coherency of the CPU caches with memory other bus masters or the instruction fetch see. More...

Macros
#define	PBL_DCACHE_LINE_SIZE   ARCH_DCACHE_LINE_SIZE
	Data cache line size in bytes, 1 without a data cache.
#define	PBL_ICACHE_LINE_SIZE   ARCH_ICACHE_LINE_SIZE
	Instruction cache line size in bytes, 1 without an instruction cache.
#define	PBL_DCACHE_ROUND_UP(size)    (((size) + PBL_DCACHE_LINE_SIZE - 1U) & ~(PBL_DCACHE_LINE_SIZE - 1U))
	size rounded up to whole data cache lines.

Functions
static void	pbl_dcache_flush_range (const void *addr, size_t size)
	Flush the data cache lines covering a range.
static void	pbl_dcache_invalidate_range (void *addr, size_t size)
	Invalidate the data cache lines covering a range.
static void	pbl_dcache_flush_invalidate_range (void *addr, size_t size)
	Flush, then invalidate the data cache lines covering a range.
static void	pbl_icache_invalidate_range (const void *addr, size_t size)
	Invalidate the instruction cache lines covering a range.

Detailed Description

Coherency of the CPU caches with memory other bus masters or the instruction fetch see.

A flush writes dirty lines back to memory and keeps them cached; an invalidate discards lines so the next access reads memory. Flush a buffer before a DMA engine reads it, and invalidate it after a DMA engine wrote it. To run code that was written as data, flush the data cache and invalidate the instruction cache over it.

Range operations cover every line the range touches, and are inline so code running while the flash is unreadable can use them. Invalidating discards writes to whatever else shares those lines, so buffers that get invalidated are aligned to PBL_DCACHE_LINE_SIZE and sized with PBL_DCACHE_ROUND_UP():

static uint8_t rx_buf[PBL_DCACHE_ROUND_UP(RX_LEN)] PBL_ALIGNED(PBL_DCACHE_LINE_SIZE);
 
pbl_dcache_invalidate_range(rx_buf, sizeof(rx_buf)); // after the DMA transfer

Without the cache an operation targets, it does nothing. The whole-cache operations exist only on CPUs that select CPU_HAS_ICACHE or CPU_HAS_DCACHE.

Macro Definition Documentation

PBL_DCACHE_LINE_SIZE

#define PBL_DCACHE_LINE_SIZE   ARCH_DCACHE_LINE_SIZE

Data cache line size in bytes, 1 without a data cache.

PBL_DCACHE_ROUND_UP

#define PBL_DCACHE_ROUND_UP

(

size

)

(((size) + PBL_DCACHE_LINE_SIZE - 1U) & ~(PBL_DCACHE_LINE_SIZE - 1U))

size rounded up to whole data cache lines.

PBL_ICACHE_LINE_SIZE

#define PBL_ICACHE_LINE_SIZE   ARCH_ICACHE_LINE_SIZE

Instruction cache line size in bytes, 1 without an instruction cache.

Function Documentation

pbl_dcache_flush_invalidate_range()

static void pbl_dcache_flush_invalidate_range ( void *  addr, size_t  size  )

static

Flush, then invalidate the data cache lines covering a range.

Parameters

addr	Start of the range.
size	Size of the range in bytes.

pbl_dcache_flush_range()

static void pbl_dcache_flush_range ( const void *  addr, size_t  size  )

static

Flush the data cache lines covering a range.

Parameters

addr	Start of the range.
size	Size of the range in bytes.

pbl_dcache_invalidate_range()

static void pbl_dcache_invalidate_range ( void *  addr, size_t  size  )

static

Invalidate the data cache lines covering a range.

Parameters

addr	Start of the range.
size	Size of the range in bytes.

pbl_icache_invalidate_range()

static void pbl_icache_invalidate_range ( const void *  addr, size_t  size  )

static

Invalidate the instruction cache lines covering a range.

Parameters

addr	Start of the range.
size	Size of the range in bytes.