SF32LB52 pin controller

Pin control controller of the SF32LB52 HPSYS pads. More...

Data Structures
struct	pbl_pinctrl_sf32lb52
	SF32LB52 pin controller. More...

Macros
#define	PBL_PINCTRL_SF32LB52_PORT_SA   0U
	SA port.
#define	PBL_PINCTRL_SF32LB52_PORT_PA   1U
	PA port.
#define	PBL_PINCTRL_SF32LB52_PIN(port, pad, fsel, pinr, field)
	Pad function, for sf32lb52_pins.h.
#define	SF32LB52_PINCTRL   (&pbl_pinctrl_sf32lb52_hpsys.ctrl)
	HPSYS pin controller.

Pad options
#define	PBL_PINCTRL_SF32LB52_PULL_UP   (PBL_PINCTRL_SF32LB52_PE | PBL_PINCTRL_SF32LB52_PS)
	Pull-up.
#define	PBL_PINCTRL_SF32LB52_PULL_DOWN   PBL_PINCTRL_SF32LB52_PE
	Pull-down.
#define	PBL_PINCTRL_SF32LB52_INPUT   PBL_PINCTRL_SF32LB52_IE
	Input buffer enabled.
#define	PBL_PINCTRL_SF32LB52_SLEW_SLOW   PBL_PINCTRL_SF32LB52_SR
	Slow slew rate, ignored on PA39-PA42.
#define	PBL_PINCTRL_SF32LB52_DRIVE_2MA   PBL_PINCTRL_SF32LB52_DS_IDX(0)
	2 mA drive.
#define	PBL_PINCTRL_SF32LB52_DRIVE_4MA   PBL_PINCTRL_SF32LB52_DS_IDX(2)
	4 mA drive.
#define	PBL_PINCTRL_SF32LB52_DRIVE_8MA   PBL_PINCTRL_SF32LB52_DS_IDX(1)
	8 mA drive, not on PA39-PA42.
#define	PBL_PINCTRL_SF32LB52_DRIVE_12MA   PBL_PINCTRL_SF32LB52_DS_IDX(3)
	12 mA drive, not on PA39-PA42.
#define	PBL_PINCTRL_SF32LB52_DRIVE_20MA   PBL_PINCTRL_SF32LB52_DS_IDX(4)
	20 mA drive, PA39-PA42 only.

Detailed Description

Pin control controller of the SF32LB52 HPSYS pads.

A pin is a pad function from sf32lb52_pins.h, such as SF32LB52_PA19_USART1_TXD, or'ed with its pad options. Every option is written when the pin is configured, so a pin without any gets no pull, a disabled input buffer, a fast slew rate and 2 mA drive:

PBL_PINCTRL_STATE_DEFINE(s_uart1_default, SF32LB52_PINCTRL,
                         SF32LB52_PA19_USART1_TXD | PBL_PINCTRL_SF32LB52_DRIVE_4MA,
                         SF32LB52_PA18_USART1_RXD | PBL_PINCTRL_SF32LB52_PULL_UP |
                             PBL_PINCTRL_SF32LB52_INPUT | PBL_PINCTRL_SF32LB52_DRIVE_4MA);

Crossbar functions (I2C, USART and timers) also route the pad in the HPSYS_CFG PINR registers, and the backup outputs of PA24-PA27 (SF32LB52_PA24_PBR_LPTIM2_OUT, ...) are driven from the RTC block. Pulls of the always-on and backup pads are mirrored there too.

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Data Structure Documentation

pbl_pinctrl_sf32lb52

struct pbl_pinctrl_sf32lb52

SF32LB52 pin controller.

Data Fields
uintptr_t	cfg	HPSYS_CFG registers, holding the PINR crossbar.
struct pbl_pinctrl_controller	ctrl	Pin controller.
uintptr_t	pad_pa	PA pad registers.
uintptr_t	pad_sa	SA pad registers.

Macro Definition Documentation

PBL_PINCTRL_SF32LB52_DRIVE_12MA

#define PBL_PINCTRL_SF32LB52_DRIVE_12MA   PBL_PINCTRL_SF32LB52_DS_IDX(3)

12 mA drive, not on PA39-PA42.

PBL_PINCTRL_SF32LB52_DRIVE_20MA

#define PBL_PINCTRL_SF32LB52_DRIVE_20MA   PBL_PINCTRL_SF32LB52_DS_IDX(4)

20 mA drive, PA39-PA42 only.

PBL_PINCTRL_SF32LB52_DRIVE_2MA

#define PBL_PINCTRL_SF32LB52_DRIVE_2MA   PBL_PINCTRL_SF32LB52_DS_IDX(0)

2 mA drive.

PBL_PINCTRL_SF32LB52_DRIVE_4MA

#define PBL_PINCTRL_SF32LB52_DRIVE_4MA   PBL_PINCTRL_SF32LB52_DS_IDX(2)

4 mA drive.

PBL_PINCTRL_SF32LB52_DRIVE_8MA

#define PBL_PINCTRL_SF32LB52_DRIVE_8MA   PBL_PINCTRL_SF32LB52_DS_IDX(1)

8 mA drive, not on PA39-PA42.

PBL_PINCTRL_SF32LB52_INPUT

#define PBL_PINCTRL_SF32LB52_INPUT   PBL_PINCTRL_SF32LB52_IE

Input buffer enabled.

PBL_PINCTRL_SF32LB52_PIN

#define PBL_PINCTRL_SF32LB52_PIN	(		port,
			pad,
			fsel,
			pinr,
			field
	)

Value:

  (((uint32_t)(pinr) << PBL_PINCTRL_SF32LB52_PINR_POS) |       \
   ((uint32_t)(field) << PBL_PINCTRL_SF32LB52_FIELD_POS) |     \
   ((uint32_t)(pad) << PBL_PINCTRL_SF32LB52_PAD_POS) |         \
   ((uint32_t)(port) << PBL_PINCTRL_SF32LB52_PORT_POS) | (uint32_t)(fsel))

Pad function, for sf32lb52_pins.h.

Parameters

port	Port.
pad	Pad.
fsel	Function select.
pinr	HPSYS_CFG PINR register offset of a crossbar function, 0 if none.
field	PINR field (signal) of a crossbar function.

PBL_PINCTRL_SF32LB52_PORT_PA

#define PBL_PINCTRL_SF32LB52_PORT_PA   1U

PA port.

PBL_PINCTRL_SF32LB52_PORT_SA

#define PBL_PINCTRL_SF32LB52_PORT_SA   0U

SA port.

PBL_PINCTRL_SF32LB52_PULL_DOWN

#define PBL_PINCTRL_SF32LB52_PULL_DOWN   PBL_PINCTRL_SF32LB52_PE

Pull-down.

PBL_PINCTRL_SF32LB52_PULL_UP

#define PBL_PINCTRL_SF32LB52_PULL_UP   (PBL_PINCTRL_SF32LB52_PE | PBL_PINCTRL_SF32LB52_PS)

Pull-up.

PBL_PINCTRL_SF32LB52_SLEW_SLOW

#define PBL_PINCTRL_SF32LB52_SLEW_SLOW   PBL_PINCTRL_SF32LB52_SR

Slow slew rate, ignored on PA39-PA42.

SF32LB52_PINCTRL

#define SF32LB52_PINCTRL   (&pbl_pinctrl_sf32lb52_hpsys.ctrl)

HPSYS pin controller.