PWM controller driver for the nRF5 PWM peripheral.
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PWM controller driver for the nRF5 PWM peripheral.
Four channels share one counter, so channels running at the same time have the same period; applying another period fails with -EBUSY. The counter runs from the 16 MHz clock with the smallest prescaler that fits the period, at most 32767 counts. The outputs are GPIOs driven to their inactive level while the PWM is stopped.
#define NRF5_GPIO_P0
Port P0.
Definition nrf5.h:40
#define PBL_GPIO(_port, _pin, _flags)
Initializer for a struct pbl_gpio.
Definition gpio.h:148
#define PBL_PWM_NRF5_DEFINE(sym, _name, _idx, _deps,...)
Define an nRF5 PWM controller.
Definition nrf5.h:63
◆ pbl_pwm_nrf5
| Data Fields |
|
struct pbl_pwm_controller |
ctrl |
PWM controller. |
|
uint8_t |
index |
Peripheral instance, from 0. |
|
struct pbl_gpio |
out[4] |
Output of each channel; unconnected channels cannot be used. |
|
struct pbl_pwm_nrf5_state * |
state |
Driver runtime state. |
◆ PBL_PWM_NRF5_DEFINE
| #define PBL_PWM_NRF5_DEFINE |
( |
|
sym, |
|
|
|
_name, |
|
|
|
_idx, |
|
|
|
_deps, |
|
|
|
... |
|
) |
| |
Value:
static struct pbl_pwm_nrf5_state sym##_nrf5_state; \
.state = &sym##_nrf5_state, \
.index = (_idx), \
}; \
PBL_DEVICE_REGISTER(sym, &sym.
ctrl.
dev)
struct pbl_gpio out[4]
Output of each channel; unconnected channels cannot be used.
Definition nrf5.h:44
struct pbl_pwm_controller ctrl
PWM controller.
Definition nrf5.h:40
nRF5 PWM controller.
Definition nrf5.h:38
struct pbl_device dev
Device.
Definition pwm.h:112
#define PBL_PWM_CONTROLLER_INIT(sym, _name, _init, _deps, _ops)
Initializer for the struct pbl_pwm_controller of controller sym.
Definition pwm.h:141
#define PBL_PWM_CONTROLLER_STATE_DEFINE(sym, _num_channels)
Define the class state of PWM controller sym, for the driver's define macro.
Definition pwm.h:127
Define an nRF5 PWM controller.
- Parameters
-
| sym | Symbol of the controller. |
| _name | Name. |
| _idx | Peripheral instance, 0 to 3. |
| _deps | Dependencies from PBL_DEVICE_DEPS(), or NULL. |
| ... | Outputs of channels 0 to 3, from PBL_GPIO(). |