sifli,sf32lb52-hpsys-rcc.h File Reference

Macros
#define	SF32LB52_HPSYS_RCC_CLK_DMAC1   0
#define	SF32LB52_HPSYS_RCC_CLK_MAILBOX1   1
#define	SF32LB52_HPSYS_RCC_CLK_PINMUX1   2
#define	SF32LB52_HPSYS_RCC_CLK_USART2   3
#define	SF32LB52_HPSYS_RCC_CLK_EZIP1   4
#define	SF32LB52_HPSYS_RCC_CLK_EPIC   5
#define	SF32LB52_HPSYS_RCC_CLK_LCDC1   6
#define	SF32LB52_HPSYS_RCC_CLK_I2S1   7
#define	SF32LB52_HPSYS_RCC_CLK_SYSCFG1   8
#define	SF32LB52_HPSYS_RCC_CLK_EFUSEC   9
#define	SF32LB52_HPSYS_RCC_CLK_AES   10
#define	SF32LB52_HPSYS_RCC_CLK_CRC1   11
#define	SF32LB52_HPSYS_RCC_CLK_TRNG   12
#define	SF32LB52_HPSYS_RCC_CLK_GPTIM1   13
#define	SF32LB52_HPSYS_RCC_CLK_GPTIM2   14
#define	SF32LB52_HPSYS_RCC_CLK_BTIM1   15
#define	SF32LB52_HPSYS_RCC_CLK_BTIM2   16
#define	SF32LB52_HPSYS_RCC_CLK_SPI1   17
#define	SF32LB52_HPSYS_RCC_CLK_SPI2   18
#define	SF32LB52_HPSYS_RCC_CLK_EXTDMA   19
#define	SF32LB52_HPSYS_RCC_CLK_SECU1   20
#define	SF32LB52_HPSYS_RCC_CLK_PDM1   21
#define	SF32LB52_HPSYS_RCC_CLK_I2C1   22
#define	SF32LB52_HPSYS_RCC_CLK_I2C2   23
#define	SF32LB52_HPSYS_RCC_CLK_PTC1   24
#define	SF32LB52_HPSYS_RCC_CLK_GPIO1   25
#define	SF32LB52_HPSYS_RCC_CLK_MPI1   26
#define	SF32LB52_HPSYS_RCC_CLK_MPI2   27
#define	SF32LB52_HPSYS_RCC_CLK_SDMMC1   28
#define	SF32LB52_HPSYS_RCC_CLK_USBC   29
#define	SF32LB52_HPSYS_RCC_CLK_I2C3   30
#define	SF32LB52_HPSYS_RCC_CLK_ATIM1   31
#define	SF32LB52_HPSYS_RCC_CLK_USART3   32
#define	SF32LB52_HPSYS_RCC_CLK_AUDCODEC   33
#define	SF32LB52_HPSYS_RCC_CLK_AUDPRC   34
#define	SF32LB52_HPSYS_RCC_CLK_GPADC   35
#define	SF32LB52_HPSYS_RCC_CLK_TSEN   36
#define	SF32LB52_HPSYS_RCC_CLK_I2C4   37
#define	SF32LB52_HPSYS_RCC_CLK_SYS   38
#define	SF32LB52_HPSYS_RCC_CLK_HCLK   39
#define	SF32LB52_HPSYS_RCC_CLK_PCLK   40
#define	SF32LB52_HPSYS_RCC_CLK_PCLK2   41
#define	SF32LB52_HPSYS_RCC_CLK_DLL1   42
#define	SF32LB52_HPSYS_RCC_CLK_DLL2   43
#define	SF32LB52_HPSYS_RCC_CLK_PERI   44
#define	SF32LB52_HPSYS_RCC_CLK_PERI_DIV2   45
#define	SF32LB52_HPSYS_RCC_CLK_MPI1_K   46
#define	SF32LB52_HPSYS_RCC_CLK_MPI2_K   47
#define	SF32LB52_HPSYS_RCC_CLK_USBC_K   48

Macro Definition Documentation

SF32LB52_HPSYS_RCC_CLK_AES

#define SF32LB52_HPSYS_RCC_CLK_AES   10

SF32LB52_HPSYS_RCC_CLK_ATIM1

#define SF32LB52_HPSYS_RCC_CLK_ATIM1   31

SF32LB52_HPSYS_RCC_CLK_AUDCODEC

#define SF32LB52_HPSYS_RCC_CLK_AUDCODEC   33

SF32LB52_HPSYS_RCC_CLK_AUDPRC

#define SF32LB52_HPSYS_RCC_CLK_AUDPRC   34

SF32LB52_HPSYS_RCC_CLK_BTIM1

#define SF32LB52_HPSYS_RCC_CLK_BTIM1   15

SF32LB52_HPSYS_RCC_CLK_BTIM2

#define SF32LB52_HPSYS_RCC_CLK_BTIM2   16

SF32LB52_HPSYS_RCC_CLK_CRC1

#define SF32LB52_HPSYS_RCC_CLK_CRC1   11

SF32LB52_HPSYS_RCC_CLK_DLL1

#define SF32LB52_HPSYS_RCC_CLK_DLL1   42

SF32LB52_HPSYS_RCC_CLK_DLL2

#define SF32LB52_HPSYS_RCC_CLK_DLL2   43

SF32LB52_HPSYS_RCC_CLK_DMAC1

#define SF32LB52_HPSYS_RCC_CLK_DMAC1   0

SF32LB52_HPSYS_RCC_CLK_EFUSEC

#define SF32LB52_HPSYS_RCC_CLK_EFUSEC   9

SF32LB52_HPSYS_RCC_CLK_EPIC

#define SF32LB52_HPSYS_RCC_CLK_EPIC   5

SF32LB52_HPSYS_RCC_CLK_EXTDMA

#define SF32LB52_HPSYS_RCC_CLK_EXTDMA   19

SF32LB52_HPSYS_RCC_CLK_EZIP1

#define SF32LB52_HPSYS_RCC_CLK_EZIP1   4

SF32LB52_HPSYS_RCC_CLK_GPADC

#define SF32LB52_HPSYS_RCC_CLK_GPADC   35

SF32LB52_HPSYS_RCC_CLK_GPIO1

#define SF32LB52_HPSYS_RCC_CLK_GPIO1   25

SF32LB52_HPSYS_RCC_CLK_GPTIM1

#define SF32LB52_HPSYS_RCC_CLK_GPTIM1   13

SF32LB52_HPSYS_RCC_CLK_GPTIM2

#define SF32LB52_HPSYS_RCC_CLK_GPTIM2   14

SF32LB52_HPSYS_RCC_CLK_HCLK

#define SF32LB52_HPSYS_RCC_CLK_HCLK   39

SF32LB52_HPSYS_RCC_CLK_I2C1

#define SF32LB52_HPSYS_RCC_CLK_I2C1   22

SF32LB52_HPSYS_RCC_CLK_I2C2

#define SF32LB52_HPSYS_RCC_CLK_I2C2   23

SF32LB52_HPSYS_RCC_CLK_I2C3

#define SF32LB52_HPSYS_RCC_CLK_I2C3   30

SF32LB52_HPSYS_RCC_CLK_I2C4

#define SF32LB52_HPSYS_RCC_CLK_I2C4   37

SF32LB52_HPSYS_RCC_CLK_I2S1

#define SF32LB52_HPSYS_RCC_CLK_I2S1   7

SF32LB52_HPSYS_RCC_CLK_LCDC1

#define SF32LB52_HPSYS_RCC_CLK_LCDC1   6

SF32LB52_HPSYS_RCC_CLK_MAILBOX1

#define SF32LB52_HPSYS_RCC_CLK_MAILBOX1   1

SF32LB52_HPSYS_RCC_CLK_MPI1

#define SF32LB52_HPSYS_RCC_CLK_MPI1   26

SF32LB52_HPSYS_RCC_CLK_MPI1_K

#define SF32LB52_HPSYS_RCC_CLK_MPI1_K   46

SF32LB52_HPSYS_RCC_CLK_MPI2

#define SF32LB52_HPSYS_RCC_CLK_MPI2   27

SF32LB52_HPSYS_RCC_CLK_MPI2_K

#define SF32LB52_HPSYS_RCC_CLK_MPI2_K   47

SF32LB52_HPSYS_RCC_CLK_PCLK

#define SF32LB52_HPSYS_RCC_CLK_PCLK   40

SF32LB52_HPSYS_RCC_CLK_PCLK2

#define SF32LB52_HPSYS_RCC_CLK_PCLK2   41

SF32LB52_HPSYS_RCC_CLK_PDM1

#define SF32LB52_HPSYS_RCC_CLK_PDM1   21

SF32LB52_HPSYS_RCC_CLK_PERI

#define SF32LB52_HPSYS_RCC_CLK_PERI   44

SF32LB52_HPSYS_RCC_CLK_PERI_DIV2

#define SF32LB52_HPSYS_RCC_CLK_PERI_DIV2   45

SF32LB52_HPSYS_RCC_CLK_PINMUX1

#define SF32LB52_HPSYS_RCC_CLK_PINMUX1   2

SF32LB52_HPSYS_RCC_CLK_PTC1

#define SF32LB52_HPSYS_RCC_CLK_PTC1   24

SF32LB52_HPSYS_RCC_CLK_SDMMC1

#define SF32LB52_HPSYS_RCC_CLK_SDMMC1   28

SF32LB52_HPSYS_RCC_CLK_SECU1

#define SF32LB52_HPSYS_RCC_CLK_SECU1   20

SF32LB52_HPSYS_RCC_CLK_SPI1

#define SF32LB52_HPSYS_RCC_CLK_SPI1   17

SF32LB52_HPSYS_RCC_CLK_SPI2

#define SF32LB52_HPSYS_RCC_CLK_SPI2   18

SF32LB52_HPSYS_RCC_CLK_SYS

#define SF32LB52_HPSYS_RCC_CLK_SYS   38

SF32LB52_HPSYS_RCC_CLK_SYSCFG1

#define SF32LB52_HPSYS_RCC_CLK_SYSCFG1   8

SF32LB52_HPSYS_RCC_CLK_TRNG

#define SF32LB52_HPSYS_RCC_CLK_TRNG   12

SF32LB52_HPSYS_RCC_CLK_TSEN

#define SF32LB52_HPSYS_RCC_CLK_TSEN   36

SF32LB52_HPSYS_RCC_CLK_USART2

#define SF32LB52_HPSYS_RCC_CLK_USART2   3

SF32LB52_HPSYS_RCC_CLK_USART3

#define SF32LB52_HPSYS_RCC_CLK_USART3   32

SF32LB52_HPSYS_RCC_CLK_USBC

#define SF32LB52_HPSYS_RCC_CLK_USBC   29

SF32LB52_HPSYS_RCC_CLK_USBC_K

#define SF32LB52_HPSYS_RCC_CLK_USBC_K   48