nRF5 QSPI

SPI memory controller driver for the nRF5 QSPI peripheral. More...

Data Structures
struct	pbl_spi_mem_nrf5_qspi
	nRF5 QSPI controller. More...

Macros
#define	PBL_SPI_MEM_NRF5_QSPI_DEFINE(sym, _name, _freq_hz, _sck, _csn, _io0, _io1, _io2, _io3)
	Define the nRF5 QSPI controller.

Functions
void	pbl_spi_mem_nrf5_qspi_irq_handler (const struct pbl_spi_mem_nrf5_qspi *qspi)
	QSPI interrupt handler, to connect with PBL_IRQ_CONNECT().

Detailed Description

SPI memory controller driver for the nRF5 QSPI peripheral.

Runs operations with up to 8 bytes after a single line opcode as custom instructions, and reads, programs and erases with the opcodes the peripheral issues itself. Its read window is the READ task, covering the whole memory. The QSPI interrupt is connected by the board:

PBL_SPI_MEM_NRF5_QSPI_DEFINE(s_qspi, "qspi", 8000000, PBL_GPIO(NRF5_GPIO_P0, 19, 0),
                             PBL_GPIO(NRF5_GPIO_P0, 17, 0), PBL_GPIO(NRF5_GPIO_P0, 20, 0),
                             PBL_GPIO(NRF5_GPIO_P0, 21, 0), PBL_GPIO(NRF5_GPIO_P0, 22, 0),
                             PBL_GPIO(NRF5_GPIO_P0, 23, 0));
PBL_IRQ_CONNECT(QSPI, 5, pbl_spi_mem_nrf5_qspi_irq_handler, &s_qspi, 0);

---

Data Structure Documentation

pbl_spi_mem_nrf5_qspi

struct pbl_spi_mem_nrf5_qspi

nRF5 QSPI controller.

Data Fields
struct pbl_gpio	csn	CSN pin.
struct pbl_spi_mem_nrf5_qspi_data *	data	Driver state.
uint32_t	freq_hz	Clock frequency, in Hz.
struct pbl_gpio	io[4]	IO0 to IO3 pins.
struct pbl_spi_mem	mem	Controller.
struct pbl_gpio	sck	SCK pin.

Macro Definition Documentation

PBL_SPI_MEM_NRF5_QSPI_DEFINE

#define PBL_SPI_MEM_NRF5_QSPI_DEFINE	(		sym,
			_name,
			_freq_hz,
			_sck,
			_csn,
			_io0,
			_io1,
			_io2,
			_io3
	)

Value:

  PBL_SPI_MEM_STATE_DEFINE(sym);                                                               \
  static struct pbl_spi_mem_nrf5_qspi_data sym##_data = {.done = PBL_SEM_INITIALIZER(0, 1)};   \
  const struct pbl_spi_mem_nrf5_qspi sym = {                                                   \
    .mem = PBL_SPI_MEM_INIT(sym, _name, nullptr, &pbl_spi_mem_nrf5_qspi_ops, 0U),              \
    .data = &sym##_data,                                                                       \
    .freq_hz = (_freq_hz),                                                                     \
    .sck = _sck,                                                                               \
    .csn = _csn,                                                                               \
    .io = {_io0, _io1, _io2, _io3},                                                            \
  };                                                                                           \
  PBL_DEVICE_REGISTER(sym, &sym.mem.dev)

Define the nRF5 QSPI controller.

Parameters

sym	Symbol of the controller.
_name	Name.
_freq_hz	Clock frequency, in Hz: 2 to 32 MHz.
_sck	SCK pin, from PBL_GPIO().
_csn	CSN pin, from PBL_GPIO().
_io0	IO0 pin, from PBL_GPIO().
_io1	IO1 pin, from PBL_GPIO().
_io2	IO2 pin, from PBL_GPIO().
_io3	IO3 pin, from PBL_GPIO().

Function Documentation

pbl_spi_mem_nrf5_qspi_irq_handler()

void pbl_spi_mem_nrf5_qspi_irq_handler

(

const struct pbl_spi_mem_nrf5_qspi *

qspi

)

QSPI interrupt handler, to connect with PBL_IRQ_CONNECT().

Parameters

qspi	Controller.