---
title: "pblprog-sifli"
canonical_url: https://developer.repebble.com/pebbleos/docs/programmers/pblprog_sifli/
last_updated: 2026-10-21
sdk_version: 4.33.1
---
# pblprog-sifli

Source: https://developer.repebble.com/pebbleos/docs/programmers/pblprog_sifli/

`pblprog-sifli` is the Pebble programmer for the SiFli SF32LB52 boards. It is a USB to serial adapter that connects to the watch’s B2B (board-to-board) connector through a flex cable, and gives the host the watch’s debug UART, a reset line and, optionally, power to charge it.

Boards:

[obelix](https://developer.repebble.com/pebbleos/docs/boards/obelix.md), [getafix](https://developer.repebble.com/pebbleos/docs/boards/getafix.md)

Host interface:

USB-C: serial port (WCH CH343P)

Target interfaces:

Debug UART, reset, VBUS

Runners:

`sftool`

Design files:

[coredevices/pblprog-sifli](https://github.com/coredevices/pblprog-sifli) (MIT)

![../../_images/pblprog-sifli-board.webp](https://developer.repebble.com/pebbleos/docs/images/pblprog-sifli-board.webp)
_pblprog-sifli-board_

![../../_images/pblprog-sifli-flex.webp](https://developer.repebble.com/pebbleos/docs/images/pblprog-sifli-flex.webp)
_pblprog-sifli-flex_

## Features

- USB-C connector, with an overcurrent fuse and ESD protection

- WCH CH343P USB to UART converter. Its I/O is powered by the watch (`VIO`), so the UART always runs at the watch’s logic level.

- Reset: the `RST` button, or the serial port’s RTS line, resets the watch. RTS reaches the reset line through the `JP1` solder jumper, bridged by default; cut it to keep the host from resetting the watch.

- Charge switch: with `CHG` on, the USB 5 V feeds the watch’s `VBUS` and charges it while connected.

- Molex SlimStack 505004-0812 B2B receptacle, for the flex cable

### Connector

| 

Pin

 | 

Signal

 | 

Description

 |
| --- | --- | --- |
| 

1

 | 

 | 

Not connected

 |
| 

2

 | 

`RESET`

 | 

Watch reset, active low

 |
| 

3

 | 

`UART_TXD`

 | 

Programmer transmit, to the watch

 |
| 

4

 | 

`GND`

 | 

Ground

 |
| 

5

 | 

 | 

Not connected

 |
| 

6

 | 

`VIO`

 | 

Watch I/O voltage, powers the UART

 |
| 

7

 | 

`VBUS`

 | 

5 V to the watch, through the `CHG` switch

 |
| 

8

 | 

`UART_RXD`

 | 

Programmer receive, from the watch

 |

### Flex cable

`pblprog-sifli-flex` has a Molex SlimStack 505006-0812 plug on each end and connects the programmer to the watch. Its pins are reversed end to end (1–4, 2–3, 5–8, 6–7), matching the orientation of the two connectors.

Generated from PebbleOS [3a7b71785](https://github.com/coredevices/pebbleos/commit/3a7b71785fd439666c4a8bc116f561140e8dec01). This page is maintained in the pebbleos repository: [docs/programmers/pblprog\_sifli.md](https://github.com/coredevices/pebbleos/blob/3a7b71785fd439666c4a8bc116f561140e8dec01/docs/programmers/pblprog_sifli.md).